这次调试项目 目前复现的问题 2.4g干扰到5g

问题就是2.4g 5g 同时发包，5g evm直接从37-38变成33-34

于是我对vco-pulling做了一个小结

VCO pulling是指当一个外部信号对振荡器的频率产生影响时，振荡器的频率将被拉动或偏移。这种现象通常会在无线电通信系统中出现，例如在无线电接收器中，接收到的信号会影响振荡器的频率。

为了避免VCO pulling，可以采取以下措施：

1. 选择合适的振荡器：选择具有高抗拉特性的振荡器，这意味着振荡器的频率不容易被外部信号影响。

2. 降低信号强度：通过使用信号衰减器或调整天线位置等方式来降低信号强度，从而减少对振荡器的影响。

3. 使用滤波器：使用合适的滤波器来过滤掉可能对振荡器频率产生影响的信号，从而减少VCO pulling的可能性。

4. 优化系统设计：在系统设计中考虑到VCO pulling的可能性，并采取相应的措施来避免或减少它的发生。

总之，避免VCO pulling需要综合考虑多种因素，包括振荡器的特性、信号强度、滤波器和系统设计等。

完整的资料介绍见星球

下面是英文的一些资料

why is vco pulling important?

Have you checked

- VCO DC power supply lines
- VCO tuning voltage input line

during transmit, using an oscilloscope?

There are names for the two different effects!

VCO Pulling: Means load variation effect on VCO phase/frequency performance

VCO Pushing: Means effects on supply and control voltages

If you inject a small tone which harmonic related to the natural frequency on the supplies (VDD,VSS, Substrate) you will get a phase reaction. If the small tone is coupled with the VCO output (synthesizer, PA) the frequency will shift.

Simulation of this effect is little tricky. Phase pertubation could be best seen by simulating two VCOs. One impacted, the other not. Make a phase difference plot. If the frequency shift should be observed you have to search for the coupling element. In most cases the substrate or supply. Simulate with and without the coupling but be careful not to change bias conditions. So only inductance change or zero DC current resistive substrate path are allowed. Otherwise the result is not true. You have to search for some kHz at some GHz!!!

vco pulling

A PLL is a control loop. It senses the phase of the VCO, and compares it to some reference. If there is a phase error, it "tunes" the VCO either up or down to minimize the phase error. A number of factors influence how quickly it corrects a phase error, if there is an overshoot or ringing if there is a sudden phase error that needs correcting, etc. 

If you have a system that is very sensitive to phase errors, and you allow the load to the VCO to suddenly change (like switching the VCO path from one load to another in a SP2T switch), then there will be a transient phase error to deal with. 

You can minimize the effect somewhat by using buffer amplifiers, attenuator pads, ferrite isolators, etc. But you might need a lot of isolation in certain systems. In any PLL that uses a digital divider, there will be a time delay before the PLL even starts to correct a transient phase error.